lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Generic Register Interface (contains various adapters)
SystemVerilog modules and classes commonly used for verification
AXI X-Bar
A simple parametrizable doorbell based mailbox
Common SystemVerilog components
Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
Pipelines the AXI path with FIFOs
APB Timer Unit
open-source Ethenet media access controller for Ariane on Genesys-2
[UNRELEASED] FP div/sqrt unit for transprecision
Simple single-port AXI memory interface
AXI Adapter(s) for RISC-V Atomic Operations