EttusResearch / uhd
The USRP™ Hardware Driver Repository
See what the GitHub community is most excited about today.
The USRP™ Hardware Driver Repository
HDL libraries and projects
Yosys + (Optional) Verific Integration
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
RISC-V System on Chip Template
IOb_SoC version of the Picorv32 RISC-V Verilog IP core
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Verilog Ethernet components for FPGA implementation
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
Wraps the NVDLA project for Chipyard integration
Verilog Configurable Cache
PicoRV32 - A Size-Optimized RISC-V CPU